What is Veriparse
Veriparse is a set of tools to help your to distribute your design in one vendor-independent verilog
module. Synthesizer delivers vendor-dependent netlists or low-level verilog, but our tools will let without
adherence qwith ASIC and FPGA vendors.
Veriparse is able to inline all the genericity of your project and flatten the whole design into one module. You
will keep the control over your design and your know-how by delivering a fully customized project to your
- Support Verilog 2001 constructions.
- Robust parser with error management.
- Support generate constructions and defparam
- Support reference of scoped variables through instance hierarchies.
- Major transformation made with Veriparse:
- Module declaration normalization,
- Parameter and localparam inlining,
- Constant folding,
- Expression evaluation,
- Loop unrolling,
- Branch selection,
- Deadcode elimination,
- Instance normalization,
- Instance flattening,