[System]Verilog Module Parser


SVModule is set of python scripts/classes to add the ability to a text editor to parse [System]Verilog module declaration and paste it as instance, parameters... It manages module imports, parameters, standard and interface ports.


SVModule is distributed under the GPLv3, the complete license description can be found here.


Proceed as follow to install the package:

$ pip3 install [--user] svmodule # --user for a local installation

Playing with svmodp, the command line interface

1. You must parse a [System]Verilog source code and generate the internal representation in a temporary file (the default file is '/tmp/svmodule-dump' under linux):

$ svmodp -c myfile.v  # Note that the script will extract information of last module in the file.

2. We can now play with the paste-as functions:

$ svmodp -i  # Paste as instance

  .add_extra_instr  (add_extra_instr),
  .add_select_instr (add_select_instr)
  .clk       (clk),
  .enable    (enable),
  .is_signed (is_signed),
  .opcode1   (opcode1),
  .opcode2   (opcode2),
  .cmode     (cmode),
  .op0       (op0),
  .op1       (op1),
  .out_en    (out_en),
  .out       (out)

3. Try the '-h' option to see the full list of paste-as functions:

usage: svmodp [-h] [-z INDENT_SIZE] [-d filename]
              [-c filename | -r | -m | -g | -i | -b | -p | -s | -o | -l | -w | -t | -y | -x]

Smart Copy & Paste of [System]Verilog files

optional arguments:
  -h, --help            show this help message and exit
  -z INDENT_SIZE, --indent-size INDENT_SIZE
                        Paste as PandaXML (default: 4)
  -d filename, --dump filename
                        parsed module file (default: /tmp/svmodule-dump)
  -c filename, --copy filename
                        (System)Verilog file (default: None)
  -r, --reverse         Reverse inputs and outputs (default: False)
  -m, --paste-as-module
                        Paste as module (default: False)
  -g, --paste-as-packages
                        Paste as packages (default: False)
  -i, --paste-as-instance
                        Paste as instance (default: False)
  -b, --paste-as-clockingblock
                        Paste as clocking block (default: False)
  -p, --paste-as-parameters
                        Paste as parameters (default: False)
  -s, --paste-as-signals
                        Paste as signals (default: False)
  -o, --paste-as-logic  Paste as logic (default: False)
  -l, --paste-as-init-latch
                        Paste as latch initialization (default: False)
  -w, --paste-as-init-wire
                        Paste as wire initialization (default: False)
  -t, --paste-as-doc-table
                        Paste as Sphinx Table (default: False)

Integration with editors

In many code editors you can wrap command line interfaces as macros:

Using SVModule as a library

If your editor supports natively python3 or if you want to use svmodule in your own project, you can just import svmodule and use directly the API without temporary files

"""Example of svmodule API use."""
from svmodule.printer import Printer
from svmodule.moddict import ModDict

# Parse a file or a string.
m = ModDict()

# Print information.
p = Printer(m)
print(p['Module'])          # Past as module
print(p['Instance'])        # Past as instance
print(p['ImportList'])      # Past as import list
print(p['ClockingBlock'])   # Past as clocking block
print(p['Parameters'])      # Past as parameters
print(p['Signals'])         # Past as signals
print(p['Logic'])           # Past as logic
print(p['InitLatch'])       # Past as init latch
print(p['InitWire'])        # Past as init wire
print(p['DocTable'])        # Past as doc table

# You can also revert the direction of I/O.